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ADT7473
HIGH LIMIT
HIGH LIMIT
TEMPERATURE
TEMPERATURE
“STICKY”
CLEARED ON READ
CLEARED ON READ
STATUS BIT
SMBALERT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
(TEMP BELOW LIMIT)
“STICKY”
STATUS BIT
SMBALERT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
(TEMP BELOW LIMIT)
Figure 29. SMBALERT and Status Bit Behavior
MASK BIT SET
INTERRUPT MASK BIT
Figure 29 shows how the SMBALERT output and sticky
status bits behave. Once a limit is exceeded, the
corresponding status bit is set to 1. The interrupt status bit
remains set until the error condition subsides and the
interrupt status register is read. The status bits are referred
to as sticky because they remain set until read by software.
This ensures that an out-of-limit event cannot be missed if
software is polling the device periodically. Note that the
SMBALERT output remains low for the entire duration that
a reading is out of limit and until the interrupt status register
has been read. This has implications on how software
handles the interrupt .
Note that THERM overtemperature events are not sticky,
resetting immediately after the overtemperature condition
ceases. This also applies to SMBALERT if associated with
an OVT event.
CLEARED
(SMBALERT RE-ARMED)
Figure 30. How Masking the Interrupt Source Affects
SMBALERT Output
Masking Interrupt Sources
Register 0x74, Interrupt Mask Register 1
Register 0x75, Interrupt Mask Register 2
These registers allow individual interrupt sources to be
masked out to prevent SMBALERT interrupts. Masking an
interrupt source prevents only the SMBALERT output from
being asserted; the appropriate status bit is set normally.
Table 29. INTERRUPT MASK REGISTER 1
(REG. 0X74)
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing
interrupts, it is recommended to handle the SMBALERT
interrupt as follows:
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt
source.
4. Mask the interrupt source by setting the
appropriate mask bit in the interrupt mask registers
(Register 0x74 and Register 0x75).
5. Take the appropriate action for a given interrupt
source.
6. Exit the interrupt handler.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 30.
Bit
7
6
5
4
3
2
1
0
Mnemonic
OOL
R2T
LT
R1T
?
V CC
V CCP
?
Description
0 when one or more alerts are
generated in Interrupt Status Register 2,
assuming all the mask bits in the
Interrupt Mask Register 2 (0x75) = 1;
SMBALERT is still asserted.
1 when one or more alerts are
generated in Interrupt Status Register 2,
assuming all the mask bits in the
Interrupt Mask Register 2 (0x75) = 1;
SMBALERT is not asserted.
1 masks SMBALERT for Remote 2
temperature.
1 masks SMBALERT for Local
temperature.
1 masks SMBALERT for Remote 1
temperature.
Unused
1 masks SMBALERT for the V CC
channel.
1 masks SMBALERT for the V CCP
channel.
Unused
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